The present invention relates to noise compensation methods and apparatuses and, in particular, to methods and apparatuses for performing noise cancellation in digital-to-analog converter applications.
With reference to FIG. 1, a conventional digital-to-analog converter (DAC) 10 produces an analog output signal (analog data) in response to a digital input signal (digital data). For example, the digital input signal may be a series of digital words containing a certain number of bits and the DAC 10 produces an analog output signal having a series of amplitudes corresponding to the digital words. The DAC 10 receives a clock signal CLK (also referred to as a word clock signal) and a voltage reference signal (Vref). The Vref signal is usually a DC level, such as 5 volts, 10 volts, etc.
The DAC 10 utilizes the DC level of the Vref signal in producing a given amplitude of the analog output signal in response to a particular digital word. Mathematically, the digital words may be thought of as fractions of unity (or percentages) that multiply the DC value of the Vref signal to produce the corresponding amplitudes of the analog output signal. For example, assuming that the digital input signal is composed of three bit digital words, the digital word 000 may represent a minimum digital magnitude and the digital word 111 may represent a digital maximum magnitude. The DAC 10 treats each digital word as a multiplier that modifies the Vref signal to produce the analog output signal. Thus, for example, the digital word 000 may be treated as a multiplier having a value of 0, the digital word 001 may be treated as a multiplier having a value of 0.125, the digital word 010 may be treated as a multiplier having a value of 0.250, etc. Thus, assuming that the Vref signal is 10 volts, the amplitude of the analog output signal in response to the digital word 010 in this example would be 0.250xc3x9710=2.5 volts.
The word clock signal CLK is utilized by the DAC 10 to establish the particular instances in time that the amplitude of the analog output signal should change in response to new digital words. Conventional DACs produce new amplitudes of the analog output signal on one of the rising and falling edges of the word clock signal CLK.
With reference to FIGS. 2A and 2B, the conventional DAC 10 exhibits undesirable performance when noise appears on the word clock signal CLK. FIG. 2A illustrates the ideal falling edges of the word clock signal CLK, which for the purposes of this discussion are utilized by the DAC 10 to indicate when the amplitude of the analog output signal should be transitioned. The ideal falling edges of the word clock signal CLK occur at t1, t2, t3, etc. In a practical circuit, however, the falling edges of the word clock signal CLK may occur at different instances due to noise. As the noise on the word clock signal CLK affects the timing of the falling edges, it is referred to herein as timing noise, but is also referred to in the art as jitter. By way of example, jitter on the word clock signal CLK may cause falling edges to occur at t1xe2x88x92xcex94t, t2xe2x88x92xcex94t, etc. As will be discussed hereinbelow, the jitter may be time invariant (e.g., producing a fixed xcex94t) or may be time variant (e.g., producing a xcex94t that changes with time).
Reference is now made to FIG. 2B which illustrates an affect that jitter on the word clock signal CLK may have on the analog output signal from the DAC 10. The solid line of FIG. 2B is intended to illustrate an ideal analog output signal from the DAC 10 in response to different digital words of the digital input signal. For simplicity, the ideal analog output signal is illustrated as a series of piecewise linear segments, although it is understood that a practical DAC produces a stepped response. Conceptually, the piecewise linear segments shown in FIG. 2B may be thought of as time integrals of the stepped output from the DAC 10 as may be produced by a filter.
Transitions in the analog output signal ideally occur at times t1, t2, t3, etc. Continuing with the example above and assuming that the digital word input to the DAC 10 was 011 just prior to time t1, the ideal analog output signal would be 3.75 volts at t1. Assuming that the digital word input to the DAC 10 just prior to time t2 was 111, the analog output signal would ideally be 10 volts at time t2. Similarly, if the digital word input to be DAC 10 just prior to time t3 was 011, then the analog output signal would ideally be 3.75 volts at time t3.
Assuming some jitter on the word clock signal CLK, however, the transitions of the analog output signal from the DAC 10 might not occur at the ideal times of t1, t2, t3, etc. Indeed, assuming a time invariant jitter of xcex94t, the transitions of the analog output signal would occur at the wrong times, e.g., t1xe2x88x92xcex94t, t2xe2x88x92xcex94t, t3xe2x88x92xcex94t, etc. In keeping with the above example, the amplitude of the analog output signal would be: (i) 3.75 volts at t1xe2x88x92xcex94t, (ii) 10.00 volts at time t2xe2x88x92xcex94t, and (iii) 3.75 volts at time t3xe2x88x92xcex94t. The piecewise linear approximation of the analog output signal as affected by jitter is shown in FIG. 2B by way of dashed line and labeled non-ideal analog output signal (jitter). Comparisons of the ideal analog output signal and the non-ideal analog signal due to jitter on the word clock signal CLK reveal that producing the right amplitudes at the wrong times is the same as producing the wrong amplitudes at the ideal times of t1, t2, t3, etc. Consequently, jitter on the word clock signal CLK produces errors in the amplitude of the analog output signal.
With reference to FIG. 2C, the Vref signal may include amplitude noise. By way of example, the amplitude noise illustrated in FIG. 2C is time invariant after time t1, although it is understood that the amplitude noise on the Vref signal may also be time variant (as will be discussed hereinbelow). Referring again to FIG. 2B, amplitude noise on the Vref signal will produce errors in the analog output signal from the DAC 10. In keeping with the digital words of 011, 111, and 011 in the above example, time invariant amplitude noise on the Vref signal (assuming no jitter on the word clock signal CLK) would produce an analog output signal from the DAC 10 having amplitudes at the ideal times of t1, t2, t3, etc. that are offset from the ideal amplitudes of 3.75 volts, 10.00 volts, 3.75 volts, respectively. In particular, the amplitude noise on the Vref signal illustrated in FIG. 2C, may be of sufficient magnitude to cause the amplitudes of the analog output signal of the DAC 10 to be 5.00 volts, 11.25 volts, and 5.00 volts at respective times t1, t2, t3, etc. These non-ideal amplitudes of the analog output signal are shown in FIG. 2B in dashed line and labeled non-ideal analog output signal (amp. noise). A comparison of the ideal analog output signal to the non-ideal output signal due to amplitude noise on the Vref signal reveals that the amplitude noise on the Vref signal produces amplitude errors in the analog output signal.
As discussed above, the jitter on the word clock signal CLK and/or the amplitude noise on the Vref signal may be time variant. Indeed, the jitter and/or the amplitude noise may contain energy at a single frequency (e.g., pure sinusoidal noise) or may contain energy at a number of discreet frequencies or even many discreet frequencies (e.g., white noise).
With reference to FIGS. 3A-3F, illustrative examples of the affects that time variant amplitude noise on the Vref signal and time variant jitter on the word clock signal CLK have on the analog output signal of the DAC 10 will now be discussed. With reference to FIG. 3A, an ideal analog output signal from the DAC 10 in response to a digital input signal consistent with a pure sine wave having a frequency of about 20 KHz is illustrated. The ideal analog output signal shown in FIG. 3A would be produced by the DAC 10 (assuming proper filtering of the stepped output) if the transitions of the word clock signal CLK occurred at ideal times (e.g., no jitter was present) and no amplitude noise was present on the Vref signal. With reference to FIG. 3B, the frequency spectrum of the ideal analog output signal from the DAC 10 (FIG. 3A) is illustrated. In particular, the frequency spectrum of the ideal analog output signal is a single magnitude of energy at 20 KHz. This magnitude is proportional to the amplitude of the ideal analog output signal.
With reference to FIG. 3C, the amplitude noise on the Vref signal may be time variant, such as amplitude noise containing energy at a single frequency of 1 KHz. Where the ideal Vref signal is flat as a function of time, the non-ideal Vref signal having amplitude noise at 1 KHz varies with time in accordance with sinusoidal properties. Assuming that the DAC 10 would produce the ideal analog output signal shown in FIG. 3A with no jitter and no amplitude noise on the Vref signal, the frequency spectrum of a non-ideal analog output signal due to amplitude noise on the Vref signal at 1 KHz would exhibit sidebands at 19 KHz and 21 KHz as shown in FIG. 3D. The magnitudes of these sidebands would be proportional to the amplitude of the amplitude noise on the Vref signal.
FIG. 3E shows a word clock signal CLK at a frequency of about 50 KHz that includes time variant jitter, where the jitter includes energy at a single frequency of 1 KHz. The dashed lines of FIG. 3E are intended to illustrate that the rising and/or falling edges of the word clock signal CLK may occur within certain time intervals, where the width of the time intervals is proportional to the xe2x80x9camplitudexe2x80x9d of the time variant jitter. Those skilled in the art will appreciate that the amplitude of the jitter may be measured using, for example, a time interval analyzer which produces an RMS value (i.e., an amplitude) representing the width of the time interval defined by the jitter. When the 1 KHz jitter shown in FIG. 3E is present on the word clock signal CLK, sidebands also appear in the frequency spectrum of the analog output signal at at least 19 KHz and 21 KHz as shown in FIG. 3D. The magnitudes of these sidebands are proportional to the amplitude of the jitter on the word clock signal CLK. Those skilled in the art will appreciate that if the jitter contains energy at more frequencies, additional sidebands will appear in the frequency spectrum of the analog output signal from the DAC 10.
Time variant jitter on the word clock signal CLK produces an additional disadvantageous affect on the frequency spectrum of the analog output signal from the DAC 10. Indeed, the magnitudes of the sidebands produced by the jitter varies as a function of the frequency content of the digital input signal of the DAC 10. For example, as shown in FIG. 3F, assuming that the word clock CLK includes sinusoidal jitter at 1 KHz, the magnitude of resultant sidebands will increase as the frequency of the digital input signal increases. Indeed, the magnitude of the sidebands increases linearly with the frequency of the digital input signal (e.g., at about 6 db per octave). Consequently, the undesirable affects of these sidebands are exacerbated at higher frequencies of the digital input signal.
The non-ideal characteristics of the analog output signal from the DAC 10 may surface in any number of situations, for example, when the DAC 10 is utilized in a CD player, a DVD player, etc. The amplitude noise on the Vref signal and/or the timing noise (jitter) on the word clock signal CLK may originate from the recording disc and/or from various noise sources within the players. With respect to the recording medium, sources of jitter and/or amplitude noise may include, but are not limited to (i) master recording medium errors (e.g., ill-defined, displaced and/or inaccurate pits and lands) that are replicated or exacerbated when the master recording medium is replicated into intermediate and/or final recording media; (ii) replication recording medium errors (e.g., warpage of intermediate and/or final replication recording media, ill-defined, displaced or inaccurate lands and pits, non-uniform replication recording media thickness or any variation in the replication recording medium itself or the process for producing the same); (iii) errors in encoding digital data onto the master recording medium (e.g., eight-to-fourteen modulation (EFM) timing errors, bandwidth errors, etc.); (iv) errors in decoding digital data from the replication recording medium (e.g., timing errors in converting the EFM data into 8 bit data, bandwidth errors, etc.); (v) circuit interface errors (e.g., analog-to-digital conversions, digital-to-analog conversions, impedance matching errors, bandwidth limitations, etc.); and (vi) circuit errors (e.g., power supply noise, switching noise, bandwidth limitations, etc.).
Although industry specifications for CDs and CD players, such as the Red Book, establish tolerances for at least some of the above-listed errors, it has been recognized that these tolerances may permit unacceptable levels of jitter and/or amplitude noise, thereby resulting in user dissatisfaction, reduced revenue, etc.
Conventional methods for reducing the errors in the analog output signal from the DAC 10 in response to jitter on the word clock signal CLK involve the use of a phase-locked loop (PLL), a shift register, and a crystal clock. The PLL is used to clock the digital input signal into the shift register and the crystal clock is used to clock the digital input signal out of the shift register. When the word clock signal CLK for the DAC 10 is derived from the crystal clock, the effects of the jitter which might otherwise be on the word clock signal CLK are theoretically reduced. It has been discovered, however, that such jitter is not completely eliminated and, in fact, such jitter may capacitively couple to the word clock signal CLK of the DAC 10 even when the word clock signal CLK is derived from the crystal clock. Moreover, other sources of jitter on the word clock signal CLK (such as capacitively coupled switching power supply noise, etc.) are not compensated for when the PLL, shift register and crystal clock method is employed.
Accordingly, there is a need in the art for new methods and/or apparatuses for compensating for jitter and/or amplitude noise in digital-to-analog applications.
In accordance with at least one aspect of the present invention, an apparatus may include: a digital-to-analog converter operable to produce an analog output signal in response to a digital input signal, a final word clock signal CLK signal, and a final voltage reference signal; and a noise compensation circuit operable to receive an initial word clock signal CLK signal and an initial voltage reference signal and to produce the final word clock signal and the final voltage reference signal such that errors in the analog output signal due to at least one of timing noise on the initial word clock signal CLK signal and amplitude noise on the initial voltage reference signal are reduced.
In accordance with at least one further aspect of the present invention, the noise compensation circuit may include: at least one of a first noise compensation circuit and a second noise compensation circuit. The first noise compensation circuit may be operable to receive the initial word clock signal CLK signal including timing information and timing noise, and to at least partly cancel the timing noise from the initial word clock signal CLK signal to produce the final word clock signal CLK signal. The second noise compensation circuit may be operable to receive the initial voltage reference signal including amplitude information and amplitude noise, and to at least partly cancel the amplitude noise from the initial voltage reference signal to produce the final voltage reference signal.
In accordance with at least one still further aspect of the present invention, the noise compensation circuit may be further operable to at least one of (i) produce the final word clock signal CLK signal by modifying the initial word clock signal CLK signal as a function of the amplitude noise such that errors in the analog output signal due to the amplitude noise are reduced, and (ii) produce the final voltage reference signal by modifying the initial voltage reference signal as a function of the timing noise such that errors in the analog output signal due to the timing noise are reduced.
In accordance with at least one still further aspect of the present invention, a method of reducing errors in an analog output signal of a digital-to-analog converter may include: receiving an initial word clock signal CLK signal having timing information and timing noise; receiving an initial voltage reference signal having amplitude information and amplitude noise; and modifying at least one of the initial voltage reference signal and the initial word clock signal CLK signal to produce a final voltage reference signal and a final word clock signal CLK signal, the final voltage reference signal and the final word clock signal CLK signal being usable by the digital-to-analog converter such that errors in the analog output signal due to at least one of amplitude noise on the initial voltage reference signal and timing noise on the initial word clock signal CLK signal are reduced.
In accordance with at least one still further aspect of the present invention, the method may include at least one of at least partly canceling the timing noise from the initial word clock signal to produce the final word clock signal, and at least partly canceling the amplitude noise from the initial voltage reference signal to produce the final voltage reference signal.
In accordance with at least one still further aspect of the present invention, the method may include at least one of modifying the initial word clock signal as a function of the amplitude noise such that errors in the analog output signal due to the amplitude noise are reduced, and modifying the initial voltage reference signal as a function of the timing noise such that errors in the analog output signal due to the timing noise are reduced.
Other features and advantages of the present invention will become apparent from the following description of the invention, which refers to the accompanying drawings.